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(R)
HI5800
Data Sheet July 2000 File Number 2938.2
12-Bit, 3MSPS, Sampling A/D Converter
The HI5800 is a monolithic, 12-bit, sampling Analog-toDigital Converter fabricated in the HBC10 BiCMOS process. It is a complete subsystem containing a sample and hold amplifier, voltage reference, two-step subranging A/D, error correction, control logic, and timing generator. The HI5800 is designed for high speed applications where wide bandwidth, accuracy and low distortion are essential.
Features
* Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 3MSPS * 12-Bit, No Missing Codes Over Temperature * Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . 1.0 LSB * Buffered Sample and Hold Amplifier * Precision Voltage Reference * Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V * 20MHz Input BW Allows Sampling Beyond Nyquist * Zero Latency/No Pipeline Delay
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Applications
* High Speed Data Acquisition Systems * Medical Imaging
Ordering Information
PART NUMBER HI5800BID HI5800JCD HI5800KCD HI5800-EV LINEARITY 1 LSB 2 LSB 1 LSB TEMP. RANGE (oC) PACKAGE PKG. NO. D40.6 D40.6
* Radar Signal Analysis * Document and Film Scanners * Vibration/Waveform Spectrum Analysis * Digital Servo Control
-40 to 85 40 Ld SBDIP 0 to 70 25 40 Ld SBDIP
Evaluation Board
Pinout
HI5800 (SBDIP) TOP VIEW
REFIN 1 ROADJ 2 RGADJ 3 AVCC 4 REFOUT 5 VIN 6 AGND 7 ADJ+ 8 ADJ- 9 AVEE 10 AVCC 11 AGND 12 AVEE 13 A0 14 CS 15 OE 16 CONV 17 DVEE 18 DGND 19 DVCC 20 40 IRQ 39 OVF 38 AVCC 37 D11 (MSB) 36 D10 35 D9 34 D8 33 DVCC 32 DGND 31 AGND 30 AVEE 29 D7 28 D6 27 D5 26 D4 25 D3 24 D2 23 D1 22 D0 (LSB) 21 AVCC
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
HI5800 Functional Block Diagram
D0 (LSB) ERROR CORRECTION OUTPUT LATCHES REFOUT 7-BIT LATCH REFERENCE D1 D2 DIGITAL OUTPUTS D10 D11 (MSB) OVF ADJ+ ADJ7-BIT DAC CONTROL LOGIC AND TIMING IRQ 7-BIT FLASH CS CONV OE AO X32
REFIN
7-BIT LATCH
VIN
S AND H
AVCC
AVEE
DVCC
DVEE
AGND
DGND
RGADJ
ROADJ
Typical Application Schematic
C23 C22 C1 +10F 0.1F 0.01F REF_IN (1) REF_OUT (5) AGND (7) AGND (12) AGND (31) DGND (19) DGND (32) VIN VIN (6) HI5800 (22) (LSB) D0 (23) D1 (24) D2 (25) D3 (26) D4 (27) D5 (28) D6 (29) D7 (34) D8 (35) D9 (36) D10 (40) IRQ (39) OVF CONV OE A0 CS CONV (17) OE (16) A0 (14) CS (15) (18) DVEE (33) DVCC (20) 0.1F + 10F 0.1F + 10F D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 IRQ OVF 10F, 0.1F, AND 0.01F CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE BNC GND
(37) (MSB) D11
AVCC R9 10K R10 10K AVEE ADJ+ (8) R11 10K ADJ- (9) RO_ADJ (2) RG_ADJ (3)
(4) AVCC (11) (21) AVCC (38) (10) AVEE (13) (30) +
0.1F
10F
0.1F
10F +
4-2
HI5800
Absolute Maximum Ratings
Supply Voltages AVCC or DVCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V AVEE or DVEE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Analog Input Pins Reference Input REFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.75V Signal Input V IN . . . . . . . . . . . . . . . . . . . . . . . . . . (REFIN +0.2V) ROADJ , RGADJ , ADJ+, ADJ- . . . . . . . . . . . . . . . . . . . . VEE to VCC Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VCC
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) JC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 40 15 Maximum Junction Temperature SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range HI5800JCD/KCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC HI5800BID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVCC = +5V, DVCC = +5V, AVEE = -5V, DVEE = -5V; Internal Reference Used, Unless Otherwise Specified HI5800JCD 0oC TO 70oC HI5800KCD, HI5800BID 0oC TO 70oC -40oC TO 85oC MAX 2 1 15 15 MIN 12 3.0 68 67 TYP 0.5 0.3 2 3 2 3 71 69 MAX 1 1 15 15 15 15 UNITS Bits LSB LSB LSB LSB LSB LSB MSPS dB dB
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS (Adjustable to Zero) Full Scale Error, FSE (Adjustable to Zero)
TEST CONDITIONS
MIN 12
TYP 0.7 0.5 2 2 69 67
fS = 3MHz, fIN = 45Hz Ramp fS = 3MHz, fIN = 45Hz Ramp (Note 8) (Note 8) JCD, KCD BID JCD, KCD BID No Missing Codes fS = 3MHz, fIN = 20kHz fS = 3MHz, fIN = 1MHz
3.0 66 65
DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale) Throughput Rate Signal to Noise Ratio (SNR) RMS Signal = -----------------------------RMS Noise Signal to Noise Ratio (SINAD) RMS Signal = ------------------------------------------------------------RMS Noise + Distortion Total Harmonic Distortion, THD Spurious Free Dynamic Range, SFDR Intermodulation Distortion, IMD Differential Gain Differential Phase Aperture Delay, tAD
fS = 3MHz, fIN = 20kHz fS = 3MHz, fIN = 1MHz fS = 3MHz, fIN = 20kHz fS = 3MHz, fIN = 1MHz fS = 3MHz, fIN = 20kHz fS = 3MHz, fIN = 1MHz fS = 3MHz, f1 = 49kHz, f2 = 50kHz (Note 3) fS = 1MHz fS = 1MHz (Note 3)
66 65 71 68 -
68 67 -74 -70 76 72 -74 0.9 0.05 12
-70 -68 -66 20
68 67 76 71 -
71 68 -85 -77 86 77 -79 0.9 0.05 12
-74 -70 -70 20
dB dB dBc dBc dBc dBc dBc % Degrees ns
4-3
HI5800
Electrical Specifications
AVCC = +5V, DVCC = +5V, AVEE = -5V, DVEE = -5V; Internal Reference Used, Unless Otherwise Specified (Continued) HI5800JCD 0oC TO 70oC PARAMETER Aperture Jitter, tAJ ANALOG INPUT Input Voltage Range Input Resistance Input Capacitance Input Current Input Bandwidth INTERNAL VOLTAGE REFERENCE Reference Output Voltage, REFOUT (Loaded) Reference Output Current Reference Temperature Coefficient REFERENCE INPUT Reference Input Range Reference Input Resistance DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, V IL Input Logic Current, IIL Digital Input Capacitance, CIN DIGITAL OUTPUTS Output Logic High Voltage, VOH Output Logic Low Voltage, V OL Output Logic High Current, IOH Output Logic Low Current, IOL Output Three-State Leakage Current, IOZ Digital Output Capacitance, COUT TIMING CHARACTERISTICS Minimum CONV Pulse, t1 CS to CONV Setup Time, t2 CONV to CS Setup Time, t3 Minimum OE Pulse, t4 CS to OE Setup Time, t5 OE to CS Setup Time, t6 IRQ Delay from Start Convert, t7 IRQ Pulse Width, t8 Minimum Cycle Time for Conversion, t9 IRQ to Data Valid Delay, t10 Minimum A0 Pulse, t11 (Note 3) (Notes 3, 5) (Notes 3, 4) (Note 3) (Note 3) (Notes 3, 5) (Note 3) (Note 3) (Note 3) JCD, KCD BID 10 10 0 15 0 0 10 190 -5 10 20 200 325 0 25 230 333 +5 10 10 0 15 0 0 10 190 180 -5 10 20 200 195 325 0 25 230 230 333 +5 ns ns ns ns ns ns ns ns ns ns ns ns VOUT = 0V, 5V IOUT = -160A IOUT = 3.2mA 2.4 -0.160 3.2 4.3 0.22 -6 6 1 10 0.4 10 2.4 -0.160 3.2 4.3 0.22 -6 6 1 10 0.4 10 V V mA mA A pF VIN = 0V, 5V VIN = 0V (Note 6) 2.0 1 5 0.8 10 2.0 1 5 0.8 10 V V A pF 2.5 200 2.6 2.5 200 2.6 V (Note 5) 2.450 2 2.500 20 2.550 2.470 2 2.500 13 2.530 V mA ppm / oC 1 2.5 3 5 1 20 2.7 10 1 2.5 3 5 1 20 2.7 10 V M pF A MHz TEST CONDITIONS (Note 3) MIN TYP 10 MAX 20 MIN HI5800KCD, HI5800BID 0oC TO 70oC -40oC TO 85oC TYP 10 MAX 20 UNITS ps
4-4
HI5800
Electrical Specifications
AVCC = +5V, DVCC = +5V, AVEE = -5V, DVEE = -5V; Internal Reference Used, Unless Otherwise Specified (Continued) HI5800JCD 0oC TO 70oC PARAMETER Data Access from OE Low, t12 LSB, Nibble Delay from A0 High, t13 MSB Delay from A0 Low, t14 CS to Float Delay, t15 Minimum CS Pulse, t16 CS to Data Valid Delay, t17 Output Fall 2 Time, tf Output Rise Time, tr IVCC IVEE IDVCC IDVEE Power Dissipation PSRR NOTES: 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. Parameter guaranteed by design or characterization and not production tested. 4. Recommended pulse width for CONV is 60ns. 5. Recommended minimum pulse width is 25ns. 7. The A0 pin VIH at -40oC may exceed 2.0V by up to 0.4V at initial power up. 8. Excludes error due to internal reference temperature drift. 6. This is the additional current available from the REFOUT pin with the REFOUT pin driving the REFIN pin. V CC, VEE 5% TEST CONDITIONS (Note 3) (Note 3) (Note 3) (Note 3) (Notes 3, 5) (Note 3) (Note 3) (Note 3) MIN 10 10 15 10 TYP 18 10 14 18 18 5 5 170 150 24 2 1.7 0.01 MAX 25 20 20 25 25 20 20 220 190 40 5 2.2 MIN 10 10 15 10 HI5800KCD, HI5800BID 0oC TO 70oC -40oC TO 85oC TYP 18 10 14 18 18 5 5 170 150 24 2 1.7 0.01 MAX 25 20 20 25 25 20 20 220 190 40 5 2.2 UNITS ns ns ns ns ns ns ns ns mA mA mA mA W % /%
POWER SUPPLY CHARACTERISTICS
Timing Diagrams
CONV t1
CS
t16 t7
IRQ
ACQUIRE N
N CONVERSION t8
DATA VALID
N - 1 DATA
N DATA
AO OE
t15 D0 - D11, OVF t12 N DATA t17
FIGURE 1. SINGLE SHOT TIMING
4-5
HI5800 Timing Diagrams
CS
(Continued)
CS
t2 CONV
t3 OE t1
t5
t6 t4
FIGURE 2A. START CONVERSION SETUP TIME
FIGURE 2B. OUTPUT ENABLE SETUP TIME
CONV CS
t7 IRQ ACQUIRE N N CONVERSION t8 t9 DATA VALID N - 1 DATA N DATA ACQUIRE N + 1 N+1 CONVERSION t10 N + 1 DATA
AO OE
t11 t13 t14
D4 - D11
D11 - D4
D3 - D0, 0000
D11 - D4
D11 - D4
D0 - D11, OVF t12
N DATA
N + 1 DATA
FIGURE 3. CONTINUOUS CONVERSION TIMING
Typical Performance Curves
80 70 60 50 dB 40 30 20 10 0 20K 200K INPUT FREQUENCY (Hz) 2M dB 90 80 70 60 50 40 30 20 10 0 20K 200K INPUT FREQUENCY (Hz) 2M
FIGURE 4. TYPICAL SNR vs INPUT FREQUENCY
FIGURE 5. TYPICAL THD vs INPUT FREQUENCY
4-6
HI5800 Typical Performance Curves
80 70 60 50 dB 40 30 20 10 0 20K 200K INPUT FREQUENCY (Hz) 2M dB
(Continued)
90 80 70 60 50 40 30 20 10 0 20K 200K INPUT FREQUENCY (Hz) 2M
FIGURE 6. TYPICAL SINAD vs INPUT FREQUENCY
FIGURE 7. TYPICAL SFDR vs INPUT FREQUENCY
12 10 8 6 4 2 0 20K ENOB dB
11.5 11.25 11.0 10.75 10.5 10.25 10.0 9.75 200K INPUT FREQUENCY (Hz) 2M 0.5 1.0 1.50 VREF (V) 2.00 2.50
FIGURE 8. TYPICAL EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY
FIGURE 9. EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE (f S = 3MHz, fIN = 20kHz)
1.0
1.0
DNL ERROR (LSB)
0.5 INL ERROR (LSB)
0.5
0
0
-0.5
-0.5
-1.0 0 1000 2000 CODE 3000 4000
-1.0 0 1000 2000 CODE 3000 4000
FIGURE 10. DIFFERENTIAL NON-LINEARITY
FIGURE 11. INTEGRAL NON-LINEARITY
4-7
HI5800 Typical Performance Curves
10 0 -25 OUTPUT LEVEL (dB) -50 -75 OUTPUT LEVEL (dB) 0 365K 730K FREQUENCY (Hz) 1.095M 1.46M
(Continued)
10 0 -25 -50 -75 -100
-100
-125 -135
-125 -135
0
365K
730K FREQUENCY (Hz)
1.095M
1.46M
FIGURE 12. FFT SPECTRAL PLOT FOR fIN = 20kHz, fS = 3MHz
10 0 -25 OUTPUT LEVEL (dB) -50 -75 -100
FIGURE 13. FFT SPECTRAL PLOT FOR fIN = 1MHz, fS = 3MHz
10 0 -25 OUTPUT LEVEL (dB) -50 49K -75 -100 -125 -135 0 18.3K 36.6K 55K 73.3K 91.6K 110K FREQUENCY (Hz) 50K
-125 -135
0
365K
730K FREQUENCY (Hz)
1.095M
1.46M
FIGURE 14. FFT SPECTRAL PLOT FOR fIN = 2MHz, f S = 3MHz
FIGURE 15. INTERMODULATION DISTORTION PLOT FOR fIN = 49kHz, 50kHz at fS = 3MHz
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 9 SYMBOL REFIN ROADJ RGADJ AV CC REFOUT NC VIN AGND ADJ+ ADJExternal Reference Input. DAC Offset Adjust (Connect to AGND If Not Used). DAC Gain Adjust (Connect to AGND If Not Used). Analog Positive Power Supply, +5V. Internal Reference Output, +2.5V. No Connection. Analog Input Voltage. Analog Ground. Sample/Hold Offset Adjust (Connect to AGND If Not Used). Sample/Hold Offset Adjust (Connect to AGND If Not Used). PIN DESCRIPTION
4-8
HI5800 Pin Descriptions
PIN # 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SYMBOL AVEE AV CC AGND AVEE A0 CS NC OE CONV DVEE DGND DVCC AV CC D0 D1 D2 D3 NC D4 D5 D6 D7 AVEE AGND DGND DVCC D8 D9 NC D10 D11 AV CC OVF IRQ Analog Negative Power Supply, -5V. Analog Positive Power Supply, +5V. Analog Ground. Analog Negative Power Supply, -5V. Output Byte Control Input, active low. When low, data is presented as a 12-bit word or the upper byte (D11 - D4) in 8-bit mode. When high, the second byte contains the lower LSBs (D3 - D0) with 4 trailing zeroes. See Text. Chip Select Input, active low. Dominates all control inputs. No Connection. Output Enable Input, active low. Convert Start Input. Initiates conversion on the falling edge. If held low, continuous conversion mode overrides and remains in effect until the input goes high. Digital Negative Power Supply, -5V. Digital Ground. Digital Positive Power Supply, +5V. Analog Positive Power Supply, +5V. Data Bit 0, (LSB). Data Bit 1. Data Bit 2. Data Bit 3. No Connection Data Bit 4. Data Bit 5. Data Bit 6. Data Bit 7. Analog Negative Power Supply, -5V. Analog Ground. Digital Ground. Digital Positive Power Supply, +5V. Data Bit 8. Data Bit 9. No Connection. Data Bit 10. Data Bit 11 (MSB). Analog Positive Power Supply, +5V. Overflow Output. Active high when either an overrange or underrange analog input condition is detected. Interrupt ReQuest Output. Goes low when a conversion is complete. (Continued) PIN DESCRIPTION
4-9
HI5800 Description
The HI5800 is a 12-bit, two-step, sampling analog-to-digital converter which uses a subranging technique with digital error correction. As illustrated in the block diagram, it uses a sample and hold front end, 7-bit, R-2R D/A converter which is laser trimmed to 14 bits accuracy, a 7-bit BiCMOS flash converter, precision bandgap reference, digital controller and timing generator, error correction logic, output latches and BiCMOS output drivers. The falling edge of the convert command signal puts the sample and hold (S/H) in the hold mode and the conversion process begins. At this point the Interrupt Request (IRQ) line is set high indicating that a conversion is in progress. The output of the S/H circuit drives the input of the 7-bit flash converter through a switch. After allowing the flash to settle, the intermediate output of the flash is stored in the latches which feed the D/A and error correction logic. The D/A reconstructs the analog signal and feeds the gain amplifier whose summing node subtracts the held signal of the S/H and amplifies the residue by 32. This signal is then switched to the flash for a second pass using the input switch. The output of the second flash conversion is fed directly to the error correction which reconstructs the twelve bit word from the fourteen bit input. The logic also decodes the overflow bit and the polarity of the overflow. The output of the error correction is then gated through the read controller to the output drivers. The data is ready on the bus as soon as the IRQ line goes low. states. If during these cycles another convert command is issued, it will be ignored until the acquire phase is complete.
Stand Alone Operation
The converter can be operated in a stand alone configuration with bus inputs controlling the converter. The conversion will be started on the negative edge of the convert (CONV) pulse as long as this pulse is less than the converter throughput rate. If the converter is given multiple convert commands, it will ignore all but the first command until such time when the acquisition period of the next cycle is complete. At this point it will start a new conversion on the first negative edge of the input command. This allows the converter to be synchronized to a multiple of a faster external clock. The new output data of the conversion is available on the same cycle at the negative edge of the IRQ pulse and is valid until the next negative edge of the IRQ pulse. Data may be accessed at any time during these cycles. It should be noted that if the data bus is kept enabled all the time (OE is low), then the data will be updating just before the IRQ goes low. During this time, the data may not be valid for a few nanoseconds.
Continuous Convert Mode
The converter can be operated at its maximum rate by taking the CONV line low (supplying the first negative edge) and holding it low. This enables the continuous convert mode. During this time, at the end of the internal acquisition period, the converter automatically starts a new conversion. The data will be valid between the IRQ negative edges. Note that there is no pipeline delay on the data. The output data is available during the same cycle as the conversion and is valid until the next conversion ends. This allows data access to both previous and present conversions in the same cycle. When initiating a conversion or a series of conversions, the last signal (CS and CONV) to arrive dominates the function. The same condition holds true for enabling the bus to read the data (CS and OE). To terminate the bus operations, the first signal (CS and OE) to arrive dominates the function.
I/O Control Inputs
The converter has four active low inputs (CS, CONV, OE and A0) and fourteen outputs (D0 - D11, IRQ and OVF). All inputs and outputs are TTL compatible and will also interface to the newer TTL compatible families. All four inputs are CMOS high input impedance stages and all outputs are BiMOS drivers capable of driving 100pF loads. In order to initiate a conversion or read the data bus, CS should be held low. The conversion is initiated by the falling edge of the CONV command. The OE input controls the output bus directly and is independent of the conversion process. The data on the bus changes just before the IRQ goes low. Therefore if the OE line is held low all the time, the data on the bus will change just before the IRQ line goes low. The byte control signal A0 is also independent of the conversion process and the byte can be manipulated anytime. When A0 is low the 12-bits and overflow word is read on the bus. The bus can also be hooked up such that the upper byte (D11 - D4) is read when A0 is low. When A0 is high, the lower byte (D3 - D0) is output on the same eight pins with trailing zeros. In order to minimize switching noise during a conversion, byte manipulations done using the A0 signal should be done in the single shot mode and A0 should be changed during the acquisition phase. For accuracy, allow sufficient time for settling from any glitches before the next conversion. Once a conversion is started, the converter will complete the conversion and acquisition periods irrespective of the input 4-10
Interrupt Request Output
The interrupt request line (IRQ) goes high at the start of each conversion and goes low to indicate the start of the acquisition. During the time that IRQ is high, the internal sample and hold is in hold mode. At the termination of IRQ, the sample and hold switches to acquire mode which lasts approximately 100ns. If no convert command is issued for a period of time, the sample and hold simply remains in acquire mode tracking the analog input signal until the next conversion cycle is initiated. The IRQ line is the only output that is not three-stateable.
Analog Input, VIN
The analog input of the HI5800 is coupled into the input stage of the Sample and Hold amplifier. The input is a high impedance bipolar differential pair complete with an ESD protection circuit. Typically it has >3M input impedance. With this high input impedance circuit, the HI5800 is easily
HI5800
interfaced to any type of op amp without a requirement for a high drive capability. Adequate precautions should be taken while driving the input from high voltage output op amps to ensure that the analog input pin is not overdriven above the specified maximum limits. For a +2.5V reference, the analog input range is 2.5V. This input range scales with the value of the external reference voltage if the internal reference is not used. For best performance, the analog ground pin next to the analog input should be utilized for signal return. Figures 16 and 17 illustrate the use of an input buffer as a level shifter to convert a unipolar signal to the bipolar input used by the HI5800. Figure 16 is an example of a noninverting buffer that takes a 0 to 2.5V input and shifts it to 2.5V. The gain can be calculated from:
V OUT R1 R2 = 1 + ------------------------ x V - --------------------- x V OFFSET IN R1 + R3 ( R1|| R3 )
VOUT VFB
is recommended that the output of the reference be decoupled with good quality capacitors to reduce the high frequency noise.
Reference Input, REFIN
The converter requires a voltage reference connected to the REFIN pin. This can be the above internal reference or it can be an external reference. It is recommended that adequate high frequency decoupling is provided at the reference input pin in order to minimize overall converter noise. A user trying to provide an external reference to a HI5800 is faced with two problems. First, the drift of the reference over temperature must be very low. Second, it must be capable of driving the 200 input impedance seen at the REFIN pin of the HI5800. Figure 18 is a recommended circuit for doing this that is capable of 2ppm/ oC drift over temperature.
HA5177 HA5002 +15 +15 + 10 k 10 10 -15 -15 +
R1|| R
R1R3 = --------------------3 R1 + R3
R2 1k R3 2k R1 2k VIN +15V
+15V + 10
REF101
0.1 C
RA
HI5800 REFIN 0.1
RB
-
LOW TC RESISTOR 0.1 VOUT HA2841 HI5800 VIN
FIGURE 18. EXTERNAL REFERENCE
VOFFSET
+ -15V
Supply and Ground Considerations
The HI5800 has separate analog and digital supply and ground pins to help keep digital noise out of the analog signal path. For the best performance, the part should be mounted on a board that provides separate low impedance planes for the analog and digital supplies and grounds. Only connect the two grounds together at one place preferably as close as possible to the part. The supplies should be driven by clean linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the HI5800. If the part is powered off a single supply then the analog supply and ground pins should be isolated by ferrite beads from the digital supply and ground pins. Also, it is recommended that the turn-on power supply sequencing be such that the analog positive supply, AICC , come up first, followed by the remaining supplies. Refer to the Application Note "Using Intersil High Speed A/D Converters" (AN9214) for additional suggestions to consider when using the HI5800.
0.1
FIGURE 16. NON-INVERTING BUFFER
Figure 17 is an example of an inverting buffer that level shifts a 0V to 5V input to 2.5V. Its gain can be calculated from:
V
VIN
OUT
= ( - R2 R1 ) x V
R1 1k R3
IN
- ( R2 R3 ) x V
R2
OFFSET
.
+15V
1k 0.1 VOUT
VOFFSET
2k
+ -15V
HA2841 0.1
HI5800 VIN
FIGURE 17. INVERTING BUFFER
Note that the correct op amp must be chosen in order to not degrade the overall dynamic performance of the circuit. Recommended op amps are called out in the figures.
Error Adjustments
For most applications the accuracy of the HI5800 is sufficient without any adjustments. In applications where accuracy is of utmost importance three external adjustments are possible: S/H offset, D/A offset and D/A gain. Figure 19 illustrates the use of external potentiometers to reduce the HI5800 errors to zero. The D/A offset (ROADJ) and S/H offset (ADJ+ and ADJ-) trims adjust the voltage offset of the transfer curve while the
Voltage Reference, REFOUT
The HI5800 has a curvature corrected internal band-gap reference generator with a buffer amplifier capable of driving up to 15mA. The band-gap and amplifier are trimmed to give +2.50V. When connected to the reference input pin REFIN , the reference is capable of driving up to 2mA externally. Further loading may degrade the performance of the output voltage. It 4-11
HI5800
D/A gain trim (RGADJ) adjusts the tilt of the transfer curve around the curve midpoint (code 2048). The 10k potentiometers can be installed to achieve the desired adjustment in the following manner.
VCC
10k 10k
ROADJ RGADJ
VEE ADJ+ 10k VEE ADJ-
Typically only one of the offset trimpots needs to be used. The offset should first be adjusted to get code 2048 centered at a desired DC input voltage such as 0V. Next the gain trim can be adjusted by trimming the gain pot until the 4094 to 4095 code transition occurs at the desired voltage (2.500V - 1.5 LSBs for a 2.5V reference). The gain trim can also be done by adjusting the gain pot until the code 0 to 1 transition occurs at a particular voltage (-2.5V + 0.5 LSBs for a 2.5V reference). If a nonzero offset is needed, then the offset pot can be adjusted after the gain trim is finished. The gain trim is simplified if an offset trim to zero is done first with a nonzero offset trim done after the gain trim is finished. The D/A offset and S/H offset trimpots have an identical effect on the converter except that the S/H offset is a finer resolution trim. The D/A offset and D/A gain typically have an adjustment range of 30 LSBs and the S/H offset typically has an adjustment range of 20 LSBs.
FIGURE 19. D/A OFFSET, D/A GAIN AND S/H OFFSET ADJUSTMENTS TABLE 1. I/O TRUTH TABLE INPUTS CS 1 0 0 0 0 0 0 X's = Don't Care TABLE 2. A/D OUTPUT CODE TABLE CODE DESCRIPTION LSB = 2 (REFIN) 4096 +FS (Full Scale) +FS - 1 LSB +3/4 FS +1/2 FS +1 LSB 0 -1 LSB -1/2 FS -3/4 FS -FS + 1 LSB -FS (NOTE) INPUT VOLTAGE REFIN = 2.5V (V) +2.5000 +2.49878 +1.8750 +1.2500 +0.00122 0.0000 -0.00122 -1.2500 -1.8750 -2.49878 -2.5000 OUTPUT DATA (OFFSET BINARY) MSB LSB CONV X 0 X X 1 X X OE X X 0 0 X X 1 A0 X X 0 1 X X X OUTPUT IRQ X X X X 0 1 X No operation. Continuous convert mode. Outputs all 12-bits and OVF or upper byte D11 - D4 in 8 bit mode. In 8-bit mode, outputs lower LSBs D3 - D0 followed by 4 trailing zeroes and OVF (See text). Converter is in acquisition mode. Converter is busy doing a conversion. Data outputs and OVF in high impedance state. FUNCTION
OVF 1 0 0 0 0 0 0 0 0 0 1
D11 1 1 1 1 1 1 0 0 0 0 0
D10 1 1 1 1 0 0 1 1 0 0 0
D9 1 1 1 0 0 0 1 0 1 0 0
D8 1 1 0 0 0 0 1 0 0 0 0
D7 1 1 0 0 0 0 1 0 0 0 0
D6 1 1 0 0 0 0 1 0 0 0 0
D5 1 1 0 0 0 0 1 0 0 0 0
D4 1 1 0 0 0 0 1 0 0 0 0
D3 1 1 0 0 0 0 1 0 0 0 0
D2 1 1 0 0 0 0 1 0 0 0 0
D1 1 1 0 0 0 0 1 0 0 0 0
D0 1 1 0 0 1 0 1 0 0 1 0
NOTE: The voltages listed above represent the ideal center of each output code shown as a function of the reference voltage.
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HI5800
If no external adjustments are required the following pins should be connected to analog ground (AGND) for optimum performance: ROADJ , RG ADJ , ADJ+, and ADJ-. (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics.
Typical Application Schematic
A typical application schematic diagram for the HI5800 is shown with the block diagram. The adjust pins are shown with 10k potentiometers used for gain and offset adjustments. These potentiometers may be left out and the respective pins should be connected to ground for best untrimmed performance.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC.
Definitions
Static Performance Definitions
Offset, Full scale, and gain all use a measured value of the internal voltage reference to determine the ideal plus and minus full scale values. The results are all displayed in LSBs.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: ENOB = (SINAD - 1.76 + V CORR) / 6.02, where: VCORR = 0.5dB.
Offset Error (VOS)
The first code transition should occur at a level 1/2 LSB above the negative full scale. Offset is defined as the deviation of the actual code transition from this point. Note that this is adjustable to zero.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak.
Full Scale Error (FSE)
The last code transition should occur for a analog input that is 11/2 LSBs below positive full scale. Full scale error is defined as the deviation of the actual code transition from this point.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present on the inputs. The ratio of the measured signal to the distortion terms is calculated. The IMD products used to calculate the total distortion are (f2-f1), (f2+f1), (2f1-f2), (2f1+f2), (2f2-f1), (2f2+f1), (3f1-f2), (3f1+f2), (3f2-f1), (3f2+f1), (2f2-2f1), (2f2+2f1), (2f1), (2f2), (2f1), (2f2), (4f1), (4f2). The data reflects the sum of all the IMD products.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the ideal value of 1 LSB. The converter is guaranteed for no missing codes over all temperature ranges.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data.
Power Supply Rejection (PSRR)
Each of the power supplies are moved plus and minus 5% and the shift in the offset and full scale error is noted. The number reported is the percent change in these parameters versus full scale divided by the percent change in the supply.
Full Power Input Bandwidth
Full power input bandwidth is the frequency at which the amplitude of the fundamental of the digital output word has decreased 3dB below the amplitude of an input sine wave. The input sine wave has a peak-to-peak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5800. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. Distortion results are quoted in dBc
4-13
HI5800 Die Characteristics
DIE DIMENSIONS: 202 mils x 283 mils x 19 mils METALLIZATION: Metal 1: Type: AlSiCu, Thickness: 6kA +1500A/-750A Metal 2: Type: AlSiCu, Thickness: 16kA +2500A/1100A PASSIVATION: Type: Sandwich Passivation - Nitride + Undoped Si Glass (USG) Thickness: Nitride - 4KA, USG - 8KA, Total - 12kA 2kA TRANSISTOR COUNT: 10K SUBSTRATE POTENTIAL (POWERED UP): VEE
Metallization Mask Layout
HI5800
D11 (MSB) REF_OUT REF_OUT RG_ADJ RO_ADJ REF_IN
AVCC AVCC
OVF
AVCC
VIN AGND D9 AGND ADJ+ ADJAVEE AVEE DVCC AVCC AVCC DGND AGND VEE AGND AVEE AVEE D6 A0 D5 CS D4 D7
D10
IRQ
D8
DVCC
DVCC
AVCC
DVEE
D1
D2
DGND
DGND
4-14
D6 (LSB)
CONV
OE
D3
HI5800 Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 -A-DBASE METAL M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b AA C A-B S D S2 Q -CA L DS b1 M (b) SECTION A-A (c) LEAD FINISH
D40.6
MIL-STD-1835 CDIP2-T40 (D-5, CONFIGURATION C) 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 D E e eA eA/2 L Q S1 S2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.510 MAX 0.225 0.026 0.023 0.065 0.045 0.018 0.015 2.096 0.620 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.95 MAX 5.72 0.66 0.58 1.65 1.14 0.46 0.38 53.24 15.75 2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 0.13 90o 40 5.08 1.78 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 4 4 5 6 7 2 8 Rev. 0 4/94
E
eA e eA/2
c
0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 0.005 90o 40 0.200 0.070 105o 0.015 0.030 0.010 0.0015
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
aaa bbb ccc M N
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